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CA3252
March 1998
Quad Gated Non-Inverting Power Driver
Description
The CA3252 is used to interface low-level logic to high current loads. Each Power Driver has four inverting switches consisting of an inverting logic input stage and an inverting low-side driver output stage. All inputs are 5V TTL/CMOS logic compatible and have a common Enable input. On-chip steering diodes are connected from each output (in pairs) to the CLAMP pins (in pairs) which may be used in conjunction with external zener diodes to protect the IC against over-voltage transients that result from inductive load switching. The CA3252 may be used in a variety of automotive and industrial control applications to drive relays, solenoids, lamps and small motors. To allow for maximum heat transfer from the chip, all ground pins on the DIP and SOIC packages are directly connected to the mounting pad of the chip. Integral heat spreading lead frames directly connect the bond pad and ground leads for good heat dissipation. In a typical application, the package is mounted on a copper PC Board. By increasing copper ground area on the PC Board, more heat is conducted away from the ground leads. The junction-to-ambient thermal resistances may be reduced to less than 40oC/W with approximately two square inches of copper area.
Features
* Four 600mA Non-Inverting Power Output Drivers * 50V and 1A Maximum Rated Power Output Drivers * VCE(SUS) Capability . . . . . . . . . . . . . . . . . . . . . . . . . 35V * Inputs Compatible With TTL or 5V CMOS Logic * Suitable For Resistive, Lamp or Inductive Loads * Inductive Clamps on Each Output * High Dissipation Power-Frame Package * Operating Temperature Ranges . . . . . . -40oC to 105oC
Applications
* Solenoids * Relays * Lamps * Steppers * Small Motors * Displays
Ordering Information System Applications
* Automotive * Appliances * Industrial Controls * Robotics
PART NUMBER CA3252E CA3252M TEMP. (oC) -40 to 105 -40 to 105 PACKAGE 16 Ld PDIP 20 Ld SOIC PKG. NO. E16.3 M20.3
Pinouts
CA3252E (PDIP) TOP VIEW
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IN A IN B ENABLE GND GND VCC IN C IN D CLAMP AB NC NC OUT B GND GND OUT C NC NC 1 2 3 4 5 6 7 8 9
CA3252M (SOIC) TOP VIEW
20 OUT A 19 IN A 18 INB 17 ENABLE 16 GND 15 GND 14 VCC 13 IN C 12 IN D 11 OUT D
OUT A CLAMP AB OUT B GND GND OUT C CLAMP CD OUT D
CLAMP CD 10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1542.2
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CA3252 Functional Block Diagram
VCC IN D CLAMP IN C OUT C V+ OUT D
GND GND ENABLE
GND GND
OUT B IN B CLAMP IN A OUT A
VCC IN D
V+
OUT D
RELAY
CLAMP IN C OUT C SOLENOID GND GND VBATT ENABLE IN B CLAMP IN A OUT A LAMP VBATT OUT B HIGH CURRENT HIGH SIDE DR MOTOR VBATT
TRUTH TABLE (Each Output) ENABLE H H L IN L H X OUT L H H
H = High, L = Low, X = Don't Care FIGURE 1. CA3252 QUAD NON-INVERTING POWER DRIVER SHOWN WITH TYPICAL APPLICATION LOADS
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CA3252
VCC CONSTANT CURRENT SOURCE ENABLE IN 11k REFERENCE VOLTAGE 1.2V
TO SUBSEQUENT STAGES
FIGURE 2. SCHEMATIC OF ONE INPUT SECTION
+5V
27k
VBATT LOAD
0.001F
12k
VCC V+ IN CLAMP ENABLE GND GND 27V CA3252 OUT
0.001F
FIGURE 3. TYPICAL LATCHED ON CIRCUIT SWITCHING CONFIGURATION. WHEN VIN IS SWITCHED LOW, THE OUTPUT IS TURNED ON (LOW).
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CA3252
Absolute Maximum Ratings
Output Voltage, VCEX . . . . . . . . . . . . . . . . . . . . . . . . . -0.7 to 50VDC Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Logic Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . .-0.7 to 15V Output Sustaining Voltage, VCE(SUS) . . . . . . . . . . . . . . . . . . 35VDC Output Current, IO (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 1ADC
Thermal Information
Thermal Resistance (Typical, Note 2) JAoC/W CA3252E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CA3252M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature Soldering (10s Max) . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 105oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. The Maximum Ambient Temperature is limited for the sustained conditions of the ICC(ON) Supply Current test with all Outputs ON. The total DC current for the CA3252 with all 4 outputs ON should not exceed 0.7A at each output for a total of (4 X 0.7A + Max. ICC) ~ 2.9A. This level of sustained current will significantly increase the on-chip temperature due to increased dissipation. Under any condition, the Absolute Maximum Junction Temperature must not exceed150oC. While any one loaded output may exceed 0.7A, the maximum rating limit is 1A. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Output Sustaining Voltage Output Leakage Current
TA = -40oC to 105oC, VCC = VEN = 5V; Unless Otherwise Specified SYMBOL VCE(SUS) ICEX VCE(SAT) TEST CONDITIONS IC = 100mA, VIN = 2V, VEN = 2V VCE = 50V, VIN = 2V, VEN = 0.8V IC = 100mA, VIN = 0.8V IC = 300mA, VIN = 0.8V IC = 600mA, VIN = 0.8V MIN 35 VIN = 0.4V IC = 600mA IC = 600mA, VIN = 4.5V IC = 600mA, All Outputs ON (Note 1) All Outputs OFF VR = 50V (Diode Reverse Voltage) IF = 0.6A IF = 1.2A -15 2 -10 0.9 MAX 100 0.3 0.5 0.8 0.8 10 -10 90 10 100 1.8 2.0 UNITS V A V V V V A V A mA mA A V V A s s V A V A
Collector to Emitter Saturation Voltage
Input Low Voltage Input Low Current Input High Voltage Input High Current Logic Supply Current, All Outputs ON Logic Supply Current, All Outputs OFF Clamp Diode Leakage Current Clamp Diode Forward Voltage
VIL IIL VIH IIH ICC(ON) ICC(OFF) IR VF
Output Current
IOUT tPHL tPLH VENL IENL VENH IENH
VIN = 0.4V, VBATT = +13V, Output Load = 10 IC = 600mA IC = 600mA
Turn-ON Propagation Delay Time Turn-OFF Propagation Delay Time Low Enable Voltage Low Enable Current High Enable Voltage High Enable Current
-
10 10 0.8 10 +250
VEN = 0.4V
-15 2.0
VEN 2V
-250
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CA3252 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E E1 e eA eB L N
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 16
2.93
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CA3252 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 12.60 7.40 MAX 2.65 0.30 0.51 0.32 13.00 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.4961 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.5118 0.2992
B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.394 0.010 0.016 20 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 20 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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